Biography

Haidar Harmanani received the B.S., M.S. and Ph.D. degrees in Computer Engineering from Case Western Reserve University, Cleveland, Ohio, in 1989, 1991 and 1994, respectively.  He is currently a professor of computer science at the Lebanese American University, .  Dr. Harmanani has previously served as the chairperson of the department of computer science and mathematics from 2002 and until 2010 and as an Associate Dean from 2010 and until 2014.

Dr. Harmanani has served on the program committees of various international conferences, including the IEEE ISCAS Conference (2016), the IEEE NEWCAS Conference (NEWCAS 2006-2016), the ABET Symposium, 2012-2014, the IEEE Midwest Symposium on Circuits and Systems, 2007, the IEEE International Conference on Electronics, Circuits, and Systems, (ICECS 2000-2016), the 14th IEEE International Conference on Microelectronics, 2002, the ACS/IEEE International Conference on Computer Systems and Applications, 2001, and the IEEE Design Automation and Test in Europe, 1998 (DATE 98). Dr. Harmanani was the General Chair of the 18th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2011) and the Technical Program Chair of the 6th International Design and Test Workshop (IDT 2011). Dr. Harmanani has been an ABET Program Evaluator (Computer Science and Computer Engineering) since 2009.

His research interests include electronic design automation, high-level synthesis, design for testability, and cluster parallel programming. He is a senior member of IEEE and a senior member of ACM.

Journal Articles

1. H. Harmanani, “An Outcome-Based Assessment Process for Accrediting Computing Programs,” European Journal of Engineering Education, Volume 42, Issue 6, pp. 844–859, Taylor and Francis, 2017.
2. S. Boughosn, F. Drouby, H. Harmanani, “A Parallel Genetic Algorithm for the Open-Shop Scheduling Problem Using Deterministic and Random Moves,” International Journal of Artificial Intelligence, Volume 14, Number 1, pp. 130-144, 2016
3. H. Salamy, H. Harmanani, “Thermal-Aware Test Scheduling using Network-on-Chip Under Multiple Clock Rates,” International Journal of Electronics, Volume 100, Issue 3, pp. 408-424, Taylor and Francis, 2013.
4. G. Dibeh, H. Harmanani, “A Stochastic Chartist-Fundamentalist Model with Time Delays,” Computational Economics, Volume 40, Number 2, pp. 105-113, Springer, 2012.
5. H. Harmanani, J. Hannouche, N. Khoury, “A Neural Networks Algorithm for the Minimum Coloring Problem using FPGAs,” International Journal of Modeling and Simulation, Volume 30, Number 4, pp. 506-513, Taylor and Francis, 2010.
6. D. Azar, H. Harmanani and R. Korkmaz, “Predicting Stability of Classes in an Object-Oriented System," Journal of Computational Methods in Science and Engineering (JCMSE), IOS Press, Holland, Volume 10, pp. 39-49, 2010.
7. M. El-Sibai, D. Platt, M. Haber, Y. Xue, S. Youhanna, R. S. Wells, H. Izaabel, M. Sanyoura, H. Harmanani, M. A. Bonab, J. Behbehani, F. Hashwa, C. Tyler-Smith, P. Zalloua, “Geographical Structure of the Y-chromosomal Genetic Landscape of the Levant: A Coastal-Inland Contrast,” Annals of Human Genetics, Volume 73, Number 6, pp. 568–581, Blackwell Publishing Ltd/University College London, 2009.
8. D. Azar, H. Harmanani, R. Korkmaz, “A Hybrid Heuristic Approach To Optimize Rule-Based Software Quality Estimation Models,” Information and Software Technology Journal, Volume 51, Number 9, pp. 1365-1376, Elsevier Science, September 2009.
9. H. Harmanani, R. Sawan, “Test Bus Assignment, Sizing, and Partitioning for System-On-Chip,” IEEE Canadian Journal on Electrical and Computer Engineering, Volume 32, Number 3, pp. 132-142, Summer 2007.
10. G. Dibeh, H. Harmanani, “Option Pricing During Post-Crash Relaxation Times,” Physica A: Statistical Mechanics and its Applications, Volume 380, pp. 357-365, Elsevier Science, July 2007.
11. H. Harmanani, A. Hajar, “Concurrent BIST Synthesis and Test Scheduling Using Genetic Algorithms,”  The International Journal of Computers and Applications, Volume 29, Number 2, pp. 132-142, Taylor and Francis, 2007.
12. H. Harmanani, H. Salamy, “A Simulated Annealing Algorithm for System-On-Chip Test Scheduling with Power and Precedence Constraints,” International Journal of Computational Intelligence and Applications, Volume 6, Number 4, pp. 511-530, Imperial College Press, December 2006.
13. H. Harmanani, H. Salamy, “Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm,” Journal of Circuits, Systems, and Computers, World Scientific Publishing Company, Volume 15, Number 3, pp. 331-349, June 2006.
14. H. Harmanani, W. Keirouz, S. Raheel, “A Rule-Based Extensible Stemmer for Information Retrieval with Application to Arabic,” The International Arab Journal of Information Technology, Volume 3, Number 3, pp. 265-272, July 2006.
15. H. Harmanani, R. Saliba, “An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis,” Journal of Circuits, Systems, and Computers, World Scientific Publishing Company, Volume 14, Number 2, pp. 347-366, April 2005.
16. H. Harmanani, P. Zouein, A. Hajar, “A Parallel Genetic Algorithm for the Geometrically Constrained Site Layout Problem with Unequal-Size Facilities,” International Journal of Computational Intelligence and Applications, Imperial College Press, Volume 4, Number 4, pp. 375-400, December 2004.
17. H. Harmanani, “A Neural Networks Algorithm for Data Path Synthesis,” International Journal of Computers and Electrical Engineering, Elsevier Science, Volume 29, Number 6, pp. 535-551, June 2003.
18. P. Zouein, H. Harmanani, A. Hajar, “A Genetic Algorithm for Solving the Site Layout Problem with Unequal Size and Constrained Facilities,” ASCE Journal of Computing in Civil Engineering, Volume 16, Issue 2, pp. 143-151, April 2002.
19. H. Harmanani, “A Parallel Neural Networks Algorithm for the Clique Partitioning Problem,” International Journal of Computers and Their Applications, Volume 9, Number 2, pp. 83-89, June 2002.
20. H. Harmanani, S. Harfoush, “A Method for Redesign for Testability at the RT Level”, in IEEE Canadian Journal of Electrical and Computer Engineering, Volume 25, Number 4, pp.163-168, October 2000.

Conferences

1. N. Anabtawi, Rony Ferzli, and H. Harmanani, “An Enhanced Light-Load Efficiency Step Down Regulator with Fine Step Frequency Scaling,” In Proceedings of the 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2695- 2698, Montreal, Canada, May 2016.
2. N. Anabtawi, Rony Ferzli, and H. Harmanani, “An All-Digital Fast Tracking Switching Converter with a Programmable Order Loop Controller for Envelope Tracking RF Power Amplifiers,” In Proceedings of the 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1690- 1693, Montreal, Canada, May 2016.
3. N. Anabtawi, Rony Ferzli, and H. Harmanani, “A Single Switcher Combined Series Parallel Hybrid Envelope Tracking Amplifier for Wideband RF Power Amplifier Applications,” In Proceedings of the 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2366- 2369, Montreal, Canada, May 2016.
4. H. Harmanani, D. Azar, G. Zgheib, and D. Kozhaya, “An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components,” In Proceedings of the 2015 IEEE 16th International Conference on Information Reuse and Integration, IEEE Computer Society, pp. 225-228, 2015.
5. A. Al-Kawam and H. Harmanani, “A Parallel GPU Implementation of the TimberWolf Placement Algorithm”, In Proceedings of the 12th International Conference on Information Technology - New Generations, IEEE Computer Society, pp. 792—795, 2015.
6. Anabtawi, Rony Ferzli, and H. Harmanani, “Efficient Shaped Quantizer Dithering Implementation for Sigma Delta Modulators,” In Proceedings of the 21st IEEE International Conference on Electronics, Circuits, and Systems, pp. 766-769, Marseille, France, 2014.
7. Helal and H. Harmanani, “Effective Solutions for the Split Delivery Vehicle Routing Problem with Time Windows,” In Proceedings of the 29th International Conference on Computers and Their Applications, pp. 315-320, 2014.
8. H. Harmanani, “A Bottom-Up Outcome-Based Learning Assessment Process for Accrediting Computing Programs,” In Proceedings of the 9th International Conference on Frontiers in Education: Computer Science and Computer Engineering, Las Vegas, 2013.
9. H. Salamy and H. Harmanani, “An Effective Solution to Thermal-Aware Test Scheduling on Network-on-Chip Using Multiple Clock Rates,” in Proceedings  of the 55th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2012), Boise, Idaho, 2012.
10. S. Baz and H. Harmanani, “An Interactive Redesign Approach for Trading Test Time, Area, and Fault Coverage in Testable Synthesis,”  Proceedings of the 27th International Conference on Computers and Their Applications, Las Vegas, Nevada, March 2012.
11. D. Azar and H. Harmanani,  “Heuristic Approaches For Optimizing The Performance Of Rule-Based Classifiers,” in Proeceedings of the IEEE International Conference on Information Reuse and Integration 2011 (IEEE IRI 2011), pp. 25-31, Las Vegas, Nevada, August 2011.
12. H. Salamy and H. Harmanani, “An Optimal Formulation for Test Scheduling Network-on-Chip Using Multiple Clock Rates”, in Proeceedings of the 24th IEEE Canadian Conference on Electrical and Computer Engineering, pp. 215-218, Niagara Falls, Canada, May 2011.
13. H. Harmanani, D. Azar, N. Helal, and W. Keirouz, “A Simulated Annealing Algorithm for the Capacitated Vehicle Routing Problem,” in Proeceedings of the 26th International Conference on Computers and Their Applications, pp. 96-101, New Orleans, March 2011.
14. R. Farah and H. Harmanani, “A Method for Efficient NoC Test Scheduling Using          Deterministic Routing,” in Proeceedings of the 23rd IEEEE International SOC Conference, pp. 395-398, Las Vegas, Nevada, September 2010.
15.  H. Harmanani and M. Kodeih, “'Estimating Test Cost During Data Path and Controller Synthesis with Low Power Overhead,” in Proceedings of the 23rd IEEE Canadian Conference on Electrical and Computer Engineering, Calgary, Canada, May 2010.
16. H. Harmanani, “Design and Implementation of a Learning Assessment Process for an International Computer Science Program,” ABET Symposium, Las Vegas, Nevada, April 2010.
17. D. Azar, H. Harmanani, R. Korkmaz, “A Hybrid Heuristic Approach To Optimize Rule-Based Software Quality Estimation Models,” in Proceedings of the 18th International Conference on Software Engineering and Data Engineering, pp.91-98, Las Vegas, Nevada, June 2009.
18. H. Harmanani, F. Drouby, S. Bou Ghosn, “A Parallel Genetic Algorithm Approach for the Open-Shop Scheduling Problem Using Deterministic Moves,” in Proceedings of the 42nd SCS/ACM Annual Simulation Symposium, pp. 1-8, San Diego, California, March 2009.
19. H. Harmanani, R. Farah, “A Method for Efficient Mapping and Reliable Routing for NoC Architectures with Minimum Bandwidth and Area,” in Proceedings of the 6th IEEE NEWCAS Conference, Montreal, Canada, June 2008.
20. H. Harmanani, R. Farah, “Integrating Wrapper Design, TAM Assignment, and Test Scheduling for SOC Test Optimization,” in Proceedings of the 6th IEEE NEWCAS Conference, Montreal, Canada, June 2008.
21. R. Farah, H. Harmanani, “An Ant Colony Optimization Approach for Test Pattern Generation,” in Proceedings of the 21st IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008), pp. 1397-1401, Niagara Falls, Canada, May 2008.
22. H. Harmanani, R. Farah, “Integrated Test Scheduling, Wrapper Design, and TAM Assignment for Hierarchical SOC” in Proceedings of the 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), pp. 1388-1391, Montreal, Canada, August 2007.
23. H. Harmanani, R. Sawan, “Test Time Minimization for System-On-Chip with Test Bus Assignment and Sizing,” in Proceedings of the 5th IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), pp. 1281-1284, Montreal, Canada, August 2007.
24. G. Dibeh, H. Harmanani, “A Stochastic Time-Delayed Speculative Model of Market Dynamics,” in the 6th International Conference on Applications of Physics in Financial Analysis, Lisbon, Portugal, July 2007.
25. H. Harmanani, R. Sawan, “A Method for Optimizing Test Bus Assignment and Sizing for System-on-a-Chip,” in Proceedings of the 20th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2007), Vancouver, Canada, pp. 90-94, April 2007.
26. H. Harmanani, H. Salamy “On Power-Constrained System-On-Chip Test Scheduling Using Precedence Relationships,” in Proceedings of the 4th IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2006), pp. 125-128, Gatineau, Canada, June 2006.
27. H. Harmanani, H. Abas, “A Method for the Minimum Coloring Problem Using Genetic Algorithms,” in Proceedings of the 17th IASTED International Conference on Modeling and Simulation (MS 2006), Montreal, Canada, pp. 487-492, May 2006.
28. H. Harmanani, B. Karablieh, “A Hybrid Distributed Test Generation Method Using Deterministic and Genetic Algorithms,” in Proceedings of the 5th IEEE International Workshop on System-on-Chip (IWSOC 2005), Banff, Alberta, Canada, pp. 317-322, July 2005.
29. H. Harmanani, H. Salamy, “Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm,” in Proceedings of the 3rd IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2005), Quebec City, Quebec, Canada, pp. 203-206, June 2005.
30. H. Harmanani, A. Hajar, “Concurrent BIST Synthesis and Test Scheduling Using Genetic Algorithms,” in Proceedings of the 8th IASTED International Conference on Artificial Intelligence and Soft Computing (ASC 2004), Marbella, Spain, pp. 410-415, September 2004.
31. H. Harmanani, W. Keirouz , S. Raheel, “A Rule-Based Extensible Stemmer for Information Retrieval With Application to Arabic,” in Proceedings of the Eighth IASTED International Conference on Artificial Intelligence and Soft Computing (ASC 2004), pp. 35-40, Marbella, Spain, September 2004.
32. H. Harmanani, A. Hajar, “An Incremental Approach for Test Scheduling and Synthesis using Genetic Algorithms,” in Proceedings of the 2004 IEEE Northeast Workshop on Circuits and  Systems (NEWCAS’2004), Montreal, Canada, pp. 69-72, June 2004.
33. H. Harmanani, W. Marrouche, “An Approach for Distributed Control in Testable High-Level Synthesis with Minimum Area and Power Overhead,” in Proceedings of the 2004 IEEE Northeast Workshop on Circuits and  Systems (NEWCAS’2004), Montreal, Canada, pp. 65-68, June 2004.
34. H. Harmanani, J. Hannouche, N. Khoury, “A Neural Networks Algorithm for the Minimum Coloring Problem using FPGAs,” in Proceedings of the IASTED International Conference on Applied Simulation and Modeling (ASM 2003), Marbella, Spain, pp. 152-156, September 2003.
35. H. Harmanani, M. Kodeih, “Concurrent BIST Cost Estimation During Data Path Allocation,” in Proceedings of the 2003 IEEE Northeast Workshop on Circuits and  Systems (NEWCAS’2003), pp. 57-60, Montreal, Canada, June 2003.
36. H. Harmanani, R. Saliba, “An Evolutionary Algorithm for the Testable Allocation Problem in High-Level Synthesis,” in Proceedings of the 9th IEEE International Conference on Electronics, Circuits, and Systems, pp. 471-474, Dubrovnik, Croatia, September 2002.
37. H. Harmanani, P. Zouein, A. Hajar, "A Parallel Genetic Algorithm for the Geometrically Constrained Site Layout Problem", in Proceedings of the 9th International Conference on Computing in Civil and Building Engineering (ICCCBE-IX), pp. 169-174, April 2002, Taipei, Taiwan.
38. H. Harmanani, R. Saliba, M. Khoury, "Testable Data Path Synthesis Using Genetic Algorithms", in Proceedings of the 2001 IEEE Canadian Conference on Electrical and Computer Engineering, May 2001, Toronto, Canada.
39. H. Harmanani, S. Harfoush, “Test Insertion at the RT Level using Functional Test Metrics,” in Proceedings of the 7th IEEE International Conference on Electronics, Circuits, and Systems, pp. 1016-1020, December 2000, Beirut, Lebanon.
40. H. Harmanani, P. Zouein, A. Hajar, “An Evolutionary Algorithm for Solving the Geometrically Constrained Site Layout Problem,” in Proceedings of the 8th ASCE International Conference on Computing in Civil and Building Engineering (ICCCBE-VIII), August 2000, pp. 1442-1449, Stanford University, USA.
41. H. Harmanani, R. Saliba, “An Evolutionary Approach for Data Path Synthesis”, in Proceedings of the 2000 IEEE Canadian Conference on Electrical and Computer Engineering, pp. 380-384, Halifax, NS, Canada.
42. H. Harmanani, “A Method for Data Path Allocation using Neural Networks”, in Proceedings of the 1999 IEEE Canadian Conference on Electrical and Computer Engineering, pp. 456-461, Edmonton, Canada.
43. H. Harmanani, S. Harfoush, “A Method for Redesign for Testability at the RT Level,” in Proceedings of the 1998 IEEE Canadian Conference on Electrical and Computer Engineering, pp. 157-160, Waterloo, ON, Canada.
44. H. Harmanani, “Testable High-Level Synthesis using VHDL, “in Proceedings of The 4th Asia-Pacific Conference on Hardware Description Languages (APCHDL'97), August 1997, Taiwan.
45. H. Harmanani, C. Papachristou, J. Carletta and M. Nourani, “A Method for Testability Insertion at the RTL—Behavioral and Structural,'' First International Test Synthesis Workshop, pp. 45-49, May 1994, Santa Barbara, USA.
46. H. Harmanani, and C. Papachristou, “An Improved Method for RTL Synthesis with Testability Trade-Offs,” in Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD’93), pp. 30-37, November 1993, Santa Clara, USA.
47. C. Papachristou, H. Harmanani, and M. Nourani, “An Approach for Redesigning in Data Path Synthesis,” in the 30th IEEE/ACM Design Automation Conference (DAC), pp. 410-425, June 1993, Dallas, USA.
48. H. Harmanani, C. Papachristou, M. Nourani and S. Chiu, “SYNTEST: An Environment for System Level Design for Test,” in Proceedings of IEEE/ACM European Design Automation Conference (Euro-DAC), pp. 402-407, September 1992, Hamburg, Germany.
49. C. Papachristou, S. Chiu, and H. Harmanani, “A Data Path Synthesis Method for Self-Testable Designs,” in the 28th IEEE/ACM Design Automation Conference (DAC), pp. 378-384, June 1991, San Francisco, USA.
50. C. Papachristou, S. Chiu, and H. Harmanani, “SYNTEST: a method for high-level SYNthesis with TESTability,” in the IEEE International Conference on Computer Design (ICCD), pp. 458-462, October 1991, Boston, USA.