Students gain experience with computer organization techniques by designing and implementing actual circuits using a high-level language, Verilog HDL and FPGAs. Course culminates in the design and simulation of a complete pipelined CPU.

Students shall be able to:

1. Describe analytically combinational and sequential circuits functions.
2. Demonstrate the ability to use FPGAs in order to implement combinational and sequential circuits.
3. Demonstrate the ability to use CAD tools such as Altera or Xilinx in order to implement and simulate circuits.
4. Demonstrate the ability to design, implement, and simulate, a given system given a set of constraints, and to evaluate the system in terms of general quality attributes and possible tradeoffs.

January 15, 2018: Spring classes begin

February 19, 2018:  Last day for early withdrawal (WI)

March 13, 2018: Deadline for Incomplete grades

March 15, 2018: Midterm Examination

March 26, 2018: Last day for withdrawal from courses (WP/WF)

April 27, 2018: Spring classes end

Professor Haidar M. Harmanani

haidar@lau.edu.lb • http://vlsi.byblos.lau.edu.lb • http://harmanani.github.io

Office Hours:

Block A • Room 810

Tuesday, Thursday • 3:00pm – 4:30pm • 8:00pm – 9:30pm or by appointment

Lecture 1: Introduction to C

Lecture 2: Boolean Algebra  and Combinational Design

Lecture 3: Combinational Blocks

Lecture 4: Introduction to Verilog

Lecture 5: More on Combinational Design Using Verilog

Lecture 6: Sequential Design

Lecture 7: Introduction to Verilog, Synthesis, and State Machines

Lecture 8: Introduction to Digital Testing

Lab 0: Introduction to C Programming

Lab 1: Introduction to C Programming Source Code

Lab 2: Using Logical Operations in C Source Code

Lab 3: Implementing a Tiny Machine using C Lab03.c

Lab 4: Extending the Tiny Machine Using C Lab04.c

Lab 6: Software Architectural Modeling

Lab Exam I: C Programming

Project Demos

Lab 7: Introduction to Quartus II Using Logic Gates Notes

DE2 115 User Manual

Altera DE2 Board Pin Table

Lab 8: Introduction to Verilog and Quartus II Using Logic Gates

Lab 9: Combinational Logic Blocks

Lab 10: Adders, Subtractors, and Multipliers

Lab 11: Switches, Lights, and Multiplexers

Lab Exam II: Verilog

Lab 12: State Elements: Circuits That Remember

Lab 13: Latches, Flip-flops, and Registers

Lab 14: Counters

Lab 15: Finite State Machines

Hardware Project: A Simple Processor: Project Demos and Presentations

All students are expected to take exams during the scheduled time slots. With the permission of the instructor, you may be allowed to take an exam at an alternate time. However, you must request this rescheduling at least 2 weeks prior to the exam date. Exceptions will naturally be made for sudden problems such as serious illnesses/injury. Since the exam schedule is being published at the beginning of the semester, scheduling conflicts (e.g., job interviews, GREs, etc.) are not legitimate reasons to miss an exam.

The final will be comprehensive and based on multiple choice questions.  It will cover C as well as Verilog.

Lab Grades

Final Grades

Programming Tutorials

• Verilog Tutorials: UCB, Harris
• ASIC World Verilog Tutorial
• TutorialsPoint C Tutorial
• C Language Tutorial
• Using Quartus II CAD Software
• C Pointers and Arrays

Programming Tools

• Free VHDL Simulator
• DE2-115 User Manual
• IEEE 754 Simulator
• PathSim
• Implementing Circuits using Altera Devices
• Physical Implementation in an FPGA
• DE2 115 Pin Assignments

• Amdahl’s Law in the Multicore Era
• Reevaluating Amdahl’s Law
• Moore’s Law
• 45nm next-generation Intel Core microarchitecture
• Multi-Core Technology