Students gain experience with computer organization techniques by designing and implementing actual circuits using a high-level language, Verilog HDL and FPGAs. Course culminates in the design and simulation of a complete pipelined CPU. Co-requisite: Corequisites: CSC 322: Computer Organization.

Students shall be able to demonstrate:

1. Students shall demonstrate an understanding of the internal organization of a computer system through assembly language
2. Students shall design and simulate the data path and the control unit of a simple computer based on an instruction set
3. Students shall demonstrate an understanding of pipelining including instruction sequencing, register value forwarding, data interlocking
4. Students shall demonstrate an understanding of the basic concepts of multiprocessor and multi-core designs.
5. Students shall demonstrate an understanding of the history and possible future of the field necessary for staying at the forefront of computing systems development.

January 15, 2018: Spring classes begin

February 19, 2018:  Last day for early withdrawal (WI)

March 13, 2018: Deadline for Incomplete grades

March 15, 2018: Midterm Examination

March 26, 2018: Last day for withdrawal from courses (WP/WF)

April 27, 2018: Spring classes end

Professor Haidar M. Harmanani

haidar@lau.edu.lb • http://vlsi.byblos.lau.edu.lb • http://harmanani.github.io

Office Hours:

Block A • Room 810

Tuesday, Thursday • 3:00pm – 4:30pm • 8:00pm – 9:30pm or by appointment

Lecture notes are made available here in PDF formats. Unless stated otherwise, all readings listed below are from D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface, ARM Edition, Morgan Kaufmann, 2017.

Lecture 1: Computer Abstraction and Technology

Lecture 2: Instructions Language of the Computer

Lecture 3: Arithmetic for Computers

Lecture 4: The Processor

Lecture 5: Large and Fast Exploiting Memory Hierarchy

Lecture 6: Parallel Processors from Client to Cloud

Additional Material: Introduction to Digital Design Using a Hardware Design Language

Advanced Material: Cluster Networking

Advanced Material: The Basics of Logic Design

Appendix B: Graphics and Computing GPUs

Appendix D: A Survey of RISC Architectures: Desktop, Server, and Embedded

Assignment 1: Computer Performance

Assignment 2: MIPS Assembly Language Programming

Assignment 3: Processor Design and Pipelining

Assignment 4: Memory Hierarchy

Project [Four Milestones]

All students are expected to take exams during the scheduled time slots. With the permission of the instructor, you may be allowed to take an exam at an alternate time. However, you must request this rescheduling at least 2 weeks prior to the exam date. Exceptions will naturally be made for sudden problems such as serious illnesses/injury. Since the exam schedule is being published at the beginning of the semester, scheduling conflicts (e.g., job interviews, GREs, etc.) are not legitimate reasons to miss an exam.

Midterm Exam

The midterm exam is scheduled for February 16, 2016: Midterm Examination. The midterm exam will be a closed book exam. In principle, all topics discussed in class (whether on the lecture notes or not) and in the assigned readings are a legitimate source for exam questions.

Previous Midterm Exam (Spring 2009)

Previous Midterm Exam Key (Spring 2009)

Final Exam

The final will be comprehensive, with roughly 1/3 of the material devoted to material covered prior to the midterm.  The exam will be on May 15, 2015 from 8:00 am - 11:00 am.

The exam will cover the following sections in the textbook:

• Chapter 1: 1.1-1.8
• Chapter 2: 2.1-2.10, 2.12-2.13
• Chapter 3: 3.1-3.5
• Chapter 4: 4.1-4.6
• Chapter 5: 5.1-5.3

Midterm Grades

Assignments Grades

Project Grades

Programming Tools

• DS-5 Development Studio
• SPIM MIPS Simulator
• ARM Reference

Programming Tutorials

• Verilog Primer
• ASIC World Verilog Tutorial
• TutorialsPoint C Tutorial

• Amdahl’s Law in the Multicore Era
• Reevaluating Amdahl’s Law
• Moore’s Law
• 45nm next-generation Intel Core microarchitecture
• Multi-Core Technology